The present disclosure relates to semiconductor device fabrication, and more specifically, to U-shaped and/or H-shaped channels for field effect transistors.
Conventional integrated circuits, such as microprocessors, storage devices, etc., include millions of circuit elements including structures such as transistors. Transistors come in a variety of shapes and forms, e.g., planar, fin-type, nanowire, etc. Irrespective of the physical configuration of the transistor device, each transistor comprises source/drain regions in a substrate, and a gate structure defining a channel positioned between the source/drain regions. Transistors may be utilized by applying a predetermined control voltage to the gate structure, causing the portion of the channel in contact with the gate structure and between the source/drain regions to become conductive. The transistors are generally either an N-type (NFET) or P-type (PFET) transistor device wherein the “N” and “P” indicate the type of dopants used to create the source/drain regions of the devices.
As discussed above, transistors come in a variety of shapes and forms. One conventional type of transistor includes a two-dimensional field effect transistor (FET), for example, a planar type transistor in which current flows through the channel region in a substrate between source/drain regions in/on the substrate adjacent to the channel. To provide better control of the current flow, three-dimensional transistor structures are becoming more commonly used as opposed to conventional two-dimensional transistors. Three-dimensional transistors are electronic switching devices in which the channel described with respect to the planar FET is replaced by a fin structure that extends outward, normal to the substrate surface, and between source/drain regions. Generally, in three-dimensional transistors the gate structure that controls current flow in the fin, wraps around three sides of the fin so as to influence the current flow from three surfaces instead of one as in planar FETs. As a result, three-dimensional transistors may exhibit faster switching performance and reduced current leakage which may improve overall performance of the transistors.
More recently, three-dimensional transistors referred to as gate-all-around (GAA) FETs, in which the gate structure surrounds all sides of the channel or fin so as to influence the current flow from every direction are being implemented in integrated circuits. GAA FETs may include channels in the form of nanowires, nanosheets, nanoelipses, etc., and stacks thereof extending between source/drain regions. GAA FET design may allow for reduced short channel effects (SCE), and an overall increase in the performance of the transistors.
One challenge associated with GAA FETs includes scaling of the channel(s). Conventional channel layouts require balancing of competing parameters of the channel (e.g., width (a.k.a., footprint), thickness, and perimeter (a.k.a., effective width, Weff)), generally at the expense of one or more of those parameters. For example, in order to increase the perimeter of a channel, the width and/or thickness of the channel may need to be increased beyond a desirable value. Increasing width and/or thickness of the channel may decrease the distance between adjacent channels, and increase the risk of electrical shorts between the structures. Increasing the thickness and/or the width of the channel may also reduce the number of channels that may be formed in a defined region of the semiconductor structure. In another example, increasing the thickness of a channel may contribute to channel bending, and decreased stability. Reducing the perimeter of a channel may also reduce the surface area of the channel in contact with the gate structure and reduce performance of the channel.